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this is information on a product in full production. november 2012 doc id 018559 rev 2 1/34 34 pm8803 high-efficiency, ieee 802.3at compliant integrated poe-pd interface and pwm controller datasheet ? production data features ieee 802.3at compliant pd interface works with power supplied from ethernet lan cables or from local auxiliary sources successful ieee802.3at layer1 classification indicator integrated 100 v, 0. 45 , 1 a hot-swap mosfet accurate 140 ma typ. inrush current level programmable classification current programmable dc current limit up to 1 a integrated high-voltage startup bias regulator thermal shutdown protection current mode pulse width modulator programmable oscillator frequency 80% maximum duty cycle with internal slope compensation support for flyback, forward, forward active clamp, flyback with synchronous rectification applications voip phones, wlan ap wimax cpes security cameras poe/poe+ powered device appliances description the pm8803 integrates a standard compliant power over ethernet (poe) interface and a current mode pwm controller to simplify the design of the power supply sections of all powered devices. the poe/poe+ interface incorporates all the functions required by the ieee 802.3at including detection, classification, undervoltage lockout (uvlo) and in-rush current limitation. the pm8803 specifically performs ieee802.3at layer1 hardware classification, providing an indication of type 2 pse successful detection to the rest of the system. the pm8803 has been designed to work with power either from the ethernet cable or from an external power source such as a wall adapter, ensuring prevalence of the auxiliary source with respect to the poe. the dc/dc section of the pm8803 features a programmable oscillator frequency, an adjustable slope compensation, dual complementary low-side drivers, programmable dead time and an internal temperature sensor. the pm8803 targets high-efficiency conversion at all load conditions supporting flyback, forward, forward with active clamp converters and synchronous rectification. htssop20 table 1. device summary part number package packing pm8803 htssop20 tube PM8803TR htssop20 tape and reel www.st.com
contents pm8803 2/34 doc id 018559 rev 2 contents 1 typical application circuits and block diagrams . . . . . . . . . . . . . . . . . . 5 1.1 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin descriptions and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 pd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 indication of successful 2-event classification . . . . . . . . . . . . . . . . . . . . . 19 4.4 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 inrush and dc current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 high-voltage startup regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 5 v bias regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 delay time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 pwm comparator / slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 auxiliary sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
pm8803 list of tables doc id 018559 rev 2 3/34 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. electrical characteristics - interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. electrical characteristics - smps section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 table 7. value of the external classification resistor for the different pd classes of power . . . . . . . 19 table 8. htssop20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of figures pm8803 4/34 doc id 018559 rev 2 list of figures figure 1. simplified application schematic for powered devices using pm8803 in forward active clamp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. simplified application schematic for powered devices using pm8803 in synchronous flyback configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. pm8803 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. block diagram of the dc/dc section of the pm8803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. pm8803: reference schematic of the poe classification logic. . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. t2p signal when connected to pse supporting 1-event classification . . . . . . . . . . . . . . . . 20 figure 8. t2p signal when connected to pse supporting 2-event classification . . . . . . . . . . . . . . . 20 figure 9. line transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. dc current vs. rdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. pwm frequency vs. rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. delay time vs. rdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13. timing relationship between output drivers as a function of dt . . . . . . . . . . . . . . . . . . . . . 26 figure 14. overload (left) and short-circuit (right) behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 15. smooth transition from poe to auxiliary source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16. htssop20 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2
pm8803 typical application circuits and block diagrams doc id 018559 rev 2 5/34 1 typical application circuits and block diagrams 1.1 application circuits figure 1. simplified application schematic for po wered devices using pm8803 in forward active clamp configuration am045091v1
typical application circuits and block diagrams pm8803 6/34 doc id 018559 rev 2 figure 2. simplified application schematic for powered devices using pm8803 in synchronous flyback configuration am045092v1 am045092v1
pm8803 typical application circuits and block diagrams doc id 018559 rev 2 7/34 1.2 block diagrams figure 3. pm8803 internal block diagram am04509 3 v1
typical application circuits and block diagrams pm8803 8/34 doc id 018559 rev 2 figure 4. block diagram of the dc/dc section of the pm8803 am045094v1
pm8803 pin descriptions and connection diagrams doc id 018559 rev 2 9/34 2 pin descriptions and connection diagrams figure 5. pin connections (top view) table 2. pin descriptions pin# name function 1ctl input of the pulse width modulator. ctl pull-up to vb is provided by an external resistor which may be used to bias an opto-coupler transistor. 2vb 5 v, up to 10 ma bias rail. this reference voltage can be used to bias an opto-coupler transistor. 3cs current sense input for current mode control and overcurrent protection. current sensing is accomplished using a dedicated current sense comparator. if the cs pin voltage exceeds 0.5 v, the gat1 pin switches low for cycle-by-cycle current limiting. cs is internally held low for 60 ns after gat1 switches high to blank leading edge current spikes. 4rtn1 power ground for the gat1 driver. this pin must be connected to rtn2 and artn. 5gat1 main gate driver output of the pwm controller. dc-dc converter gate driver output with 1 a peak sink-source current capability. (5 ohm typ mosfets). 6vc output of the internal high-voltage regulator. when the auxiliary transformer winding (if used) raises the voltage on this pin above the 8 v typ. regulation set point, the internal regulator will shutdown, reducing the internal power dissipation. filter this pin with a 1f typ. connected to ground. 7gat2 secondary gate driver output. aux gate driver output for active clamp or synchronous rectification designs. 1 a peak sink-source current capability (5 ohm typ. mosfets). 8artn analog pwm supply ground. rtn for sensitive analog circuitry including the smps current limit amplifier. 1 2 3 4 s a dccl fr s t2p rtn1 c s vb ctl 11 12 det s p cl s dt artn gat2 vc gat1 5 6 7 8 1 3 14 15 16 v ss rtn2 9 10 vdd vdd 17 1 8 19 20 am045095v1
pin descriptions and connection diagrams pm8803 10/34 doc id 018559 rev 2 9rtn2 power ground for the secondary gate driver. this pin is also connected to the drain of the internal current limiting power mosfet which closes vss to the return path of the dc-dc converter. this pin must be connected to rtn1 and artn 10 vss system low potential input. diode "or'd" to the rj45 connector and pse's -48v supply, it is the more negative input potential. 11 vdd system high potential input. the diode "or" of several lines entering the pd, it is the most positive input potential. 12 vdd system high potential input. the diode "or" of several lines entering the pd, it is the most positive input potential. 13 det detection resistor pin. connect the signature resistance between the det pin and vdd. current will flow through the resistor only during the detection phase. this pin is 100v rated with negligible resistance with respect to the external 24.9k . 14 sp front auxiliary startup pin. pulling up this pin to the auxiliary source will change the internal uvlo set- tings and allow pd to be powered with voltage lower than nominal poe volt- ages. default inrush and dc current protection are active. use a resistor voltage divider from the auxiliary voltage to vss to connect this low voltage rating pin. connect this pin to vss if not used. 15 cls classification resistor pin. connect the classification programming resistor from this pin to vss. 16 dccl dc current limit. a resistor between this pin and vss will set the current limit for the interface section of pm8803. it can be set to exceed the ieee802.3at current limit. leave the pin open for standard ieee 802.3at applications. 17 sa rear auxiliary startup pin. pulling up this pin will give high priority to an auxiliary power source like an external wall adapter. use a resistor voltage divider from the auxiliary volt- age to artn to connect this low voltage rating pin. connect this pin to artn if not used. 18 dt delay time set. a resistor connected from this pin to artn sets the delay time between gat1 and gat2. this pin cannot be left open. 19 frs switching frequency set. an external resistor connected from frs to artn sets the oscillator fre- quency. table 2. pin descriptions (continued) pin# name function
pm8803 pin descriptions and connection diagrams doc id 018559 rev 2 11/34 20 t2p successful 2-event classification indicator. t2p open drain signal assertion happens when powered by a pse performing a 2-event classification. t2p is an active-low signal. ep exposed pad. connect this to a pcb copper plane to improve heat dissipation; must be electrically connected to vss. table 2. pin descriptions (continued) pin# name function
electrical specifications pm8803 12/34 doc id 018559 rev 2 3 electrical specifications 3.1 absolute maximum ratings table 3. absolute maximum ratings note: absolute maximum ratings are limits beyond which damage to the device may occur. 3.2 thermal data table 4. thermal data 3.3 electrical characteristics vdd = 48 v, vc = not loaded, cvc = 1 f, vb = not loaded, cvb = 1 f, gat1 and gat2 = not loaded, t a = 25 c unless otherwise specified. values in bolded type apply over the full operating ambient temperature range. parameter value unit vdd, det, artn to vss -0.3 to 100 v cls, sp, dccl to vss -0.3 to 3.6 v vc to artn -0.3 to 16 v gat1, gat2, t2p to artn -0.3 to vc+0.3 v ctl, vb, dt to artn -0.3 to 5.5 v frs, sa, cs to artn -0.3 to 3.6 v rtn1, rtn2 to artn -0.3 to 0.3 v esd hbm 2 kv esd cdm 500 v operating junction temperature (1) 1. internally limited to 160 c typ with inte rnal overtemperatur e protection circuit. -40 to 150 c storage temperature -40 to 150 c symbol parameter value unit r thja max thermal resistance junction to ambient (1) 1. package mounted on a 4-layer board ( 2 signals + 2 power s ), cu thickness 35 micron, with 6-8 vias on the exposed pad copper area connected to an inner power plane 40 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j operative junction temperature range -40 to 125 c t a operative ambient temperature range -40 to 85 c
pm8803 electrical specifications doc id 018559 rev 2 13/34 table 5. electrical characteristics - interface section symbol parameter test conditions min. typ. max. unit detection and classification signature enable vdd rising 1.5 v signature pull-down resistance within signature range 150 350 w signature disable vdd rising 10.3 10.8 11.3 v classification enable vdd rising 11.3 12 12.7 v classification turn-off vdd rising 21.5 23.0 24.5 v mark event threshold / classification turn-off vdd falling 9 10 11 v classification reset threshold vdd falling 3 4 5 v cls voltage within classification range with 44 ma load 1.3 1.4 1.5 v cls max current capability within classification range with cls pin grounded 50 65 80 ma bias current idd vdd supply current during detection vdd = 8 v 10 a vdd supply current during classification 900 1200 a vdd supply current during mark event 500 800 1100 a undervoltage lockout v uvlo_r uvlo release vin rising 34 35 36.5 v v uvlo_f uvlo lockout vin falling 30 31 32.5 v uvlo hysteresis 3.5 4 4.5 v hot-swap mosfet r dson mosfet resistance 0.45 1 default inrush current limit 125 140 155 ma default dc current limit 590 640 690 ma
electrical specifications pm8803 14/34 doc id 018559 rev 2 dccl adjust dccl voltage 1.4 v dc current limit selection range 140 1000 ma adjustable dc current limit precision r dccl = 30 to 150 k -15 +15 % inrush to dc current switchover v ds required for inrush to dc switchover v ds falling - hot-swap mosfet closing. 1.35 1.50 1.75 v v gs required for inrush to dc switchover v ds falling - hot-swap mosfet closing. guaranteed by design 2v v ds required for inrush to dc switchover v ds rising - hot-swap mosfet opening 11 12 13 v front auxiliary source detection sp threshold voltage rising 1.0 1.1 1.2 v sp hysteresis 200 mv minimum vdd voltage for front aux. operations 13 15 v table 5. electrical characteristics - interface section (continued) symbol parameter test conditions min. typ. max. unit
pm8803 electrical specifications doc id 018559 rev 2 15/34 table 6. electrical characteristics - smps section symbol parameter test conditions min. typ. max. unit oscillator f osc frequency accuracy in the range 100 to 500 khz +/-10 % frequency programmability r frs = 100 k 220 245 270 khz r frs = 47.5 k 445 495 545 khz frequency range 100 1000 khz frs voltage 1.20 1.25 1.30 v delay time gat1 to gat2 delay time r dt = 20 k , gat1and gat2 open 32 ns r dt = 200 k , gat1and gat2 open 320 ns dt voltage 1.20 1.25 1.30 v soft-start t ss soft-start time over ctl full range (0 to 3 v), at f osc = 250 khz 12.3 ms current limit delay to output guaranteed by design 20 ns cycle-by-cycle current limit threshold voltage 0.44 0.50 0.56 v leading edge blanking time 45 60 75 ns slope compensation current sourced by cs pin 45 a pwm comparator delay to output guaranteed by design 25 ns minimum duty cycle ctl = 0, cs = 0 0 % maximum duty cycle ctl = 2 v, cs = 0, f osc = 250 khz 75 80 85 % ctl to pwm gain guaranteed by design 1 : 4 ctl operative range 1 3 v output driver gat1 output high i gd = 100 ma vc- 0.25 vc-0.5 v output low i gd = -100 ma 0.25 0.5 v fall time c load = 3.3 nf, vc = 10 v guaranteed by design 40 ns rise time c load = 3.3 nf, vc = 10 v guaranteed by design 45 ns
electrical specifications pm8803 16/34 doc id 018559 rev 2 peak source current c load = 3.3 nf, vc = 10 v guaranteed by design 800 ma peak sink current c load = 3.3 nf, vc = 10 v guaranteed by design 1a output driver gat2 output high i gd = 100 ma vc- 0.25 vc-0.5 v output low i gd = -100 ma 0.25 0.5 v fall time c load = 3.3 nf, vc = 10 v guaranteed by design 40 ns rise time c load = 3.3 nf, vc = 10 v guaranteed by design 45 ns peak source current c load = 3.3 nf, vc = 10 v guaranteed by design 800 ma peak sink current c load = 3.3 nf, vc = 10 v guaranteed by design 1a thermal shutdown shutdown temp. always active; guaranteed by design 160 c shutdown hyst. 30 c vc regulation vc internal default 7.7 8.0 8.3 v vc current limit ib = 0; gat1, gat2 = open 14 20 ma vc uvlo internal default uvlo, release vc rising vc-0.3 v internal default; uvlo, lockout vc falling 5.7 6.0 6.3 v vc regulator dropout ic = 10 ma; gat1, gat2 = open 2 v vb regulation vb internal default 4.85 5.0 5.15 v vb current limit ic = 0; gat1, gat2 = open 5 10 ma vb sink current capability 1 ma rear auxiliary source detection sa threshold 1.1 1.2 1.3 v sa hysteresis 180 mv table 6. electrical characteristics - smps section (continued) symbol parameter test conditions min. typ. max. unit
pm8803 electrical specifications doc id 018559 rev 2 17/34 note: 1 minimum and maximum limits are guaranteed by test, design, or statistical correlation.typical values represent the most likely parametric norm at t a = 25 c, and are provided for reference only. 2 device thermal limitations could limit useful operating range. 3 the vc regulator is intended for internal use only as the startup supply of the pm8803; any additional external vc current, including the vb regulator current and external mosfet driving current, has to be limited within the specified max current limit. minimum vdd voltage for rear aux. operations 13 15 v t2p flag t2p pull-up current 20 25 30 a t2p pull-down resistance 45 75 device current consumption vd quiescent current vd > v uvlo_r, vc = 12 v, ctl = 0 1.25 1.5 ma vc quiescent current vd > v uvlo_r, vc = 12 v, ctl = 0 2 2.5 ma table 6. electrical characteristics - smps section (continued) symbol parameter test conditions min. typ. max. unit
pd interface pm8803 18/34 doc id 018559 rev 2 4 pd interface 4.1 detection in power over ethernet systems, the power sourcing equipment (pse) senses the ethernet connection to detect whether the powered device (pd) is plugged into the cable termination by applying a small voltage (2.7 v to 10 v) on the ethernet cable and measuring the equivalent resistance in at least two consecutive steps. during this phase, the pd must present a resistance between 23.75 k and 26.25 k . the signature resistor must be connected between the det and vdd pins. this resistor is in-series to a pass transistor (see figure 3 ) enabled only during the detection phase. no current is flowing through the signature resistor for the rest of the operative phases (classification and turn-on). the value of the detection resistance has to be selected also taking into account the typical drop in voltage of the diode bridges. the typical value that can be used in most case is 24.9 k . during detection, most of the circuits inside the pm8803 are disabled to minimize the offset current. 4.2 classification the classification phase in a poe network is the feature that allows pse to plan and allocate the available power to the appliances connected to various ethernet ports. the pm8803 complies with both ieee802.3at 1-event and 2-event classification schemes. 1-event classification in ieee802.3at is the same as specified in the ieee 802.3af standard, which divides the power levels below 12.95 w into 5 classes (class 0 to class 4). while class 4 was reserved in ieee802.3af, in ieee802.3at class 4 identifies type2 pds requiring up to 25.5 w. a type2 pd is a pd that provides a class 4 signature during physical layer classification, understands 2-event classification and is capable of data link layer classification. figure 8 represent the voltage at the input of the pd when connected to a pse performing 2-event classification. a type2 pd will present in both classification events a class 4 current while during the so called ?mark-event?, between the 2 classification fingers, the pd will present an invalid signature resistance. to support the classification function, an equivalent programmable constant current generator has been implemented. figure 6 depicts a primary schematic of the classification circuit. following the successful completion of the detection phase, the voltage of the cls pin is set to the 1.4 v voltage reference and a pass transistor connects the vin pin to the cls pin.
pm8803 pd interface doc id 018559 rev 2 19/34 figure 6. pm8803: reference schematic of the poe classification logic the classification resistor can be disconnected for the following reasons: ? the classification has been successfully completed ? an auxiliary power source has been connected ? the device is in thermal protection designers can set the current by changing the value of the external resistor according to the following table. 4.3 indication of successful 2-event classification the pm8803 is capable of recognizing whether it is connected to a pse performing 1-event or 2-event physical layer classification by asserting the t2p signal. t2p is an open-drain, active-low signal which is asserted in case a successful 2-event classification event is completed. t2p will be asserted as soon as the high-voltage startup regulator output is stable. ( see figure 7 and figure 8 for timing sequences). if the pm8803 sees a 1-event classification or no classification, t2p is pulled up and the main circuit in the pd can try to establish an lldp connection to negotiate the power. no lldp response from the pse means that the pd is connected to a type1 pse, and only 13 w input power will be available. table 7. value of the external classification resistor for the different pd classes of power class pd max average power (w) r cls ( ) 013 2k 13.84 150 26.49 80.6 313 51.1 425.5 35.6 vdd vss + - 1.4v r class cls en thermal_alarm class_enable aux_enabled pm8803 am045096v1
pd interface pm8803 20/34 doc id 018559 rev 2 a low t2p signal after the turn-on phase of the poe means that the pd is connected to a type2, 2-event physical layer classification pse which may allocate power either through further lldp negotiation or directly feedthe pd with the required power. in isolated applications, the main circuits and the pm8803 are at both sides of the galvanic isolation. the t2p signal is normally connected to an optocoupler to pass the type 2, 2-event pse detection information to the main circuit in the pd system. figure 7. t2p signal when connected to pse supporting 1-event classification figure 8. t2p signal when connected to pse supporting 2-event classification time p s e volt a ge idle or m a rk r a nge cl ass ific a tion r a nge on r a nge detection time output voltage s oft s t a rt v time t2p ( 8 02. 3a f) v t2p s t ab le b efore o u tp u t s oft- s t a rt am045097v1 time p s e volt a ge idle or m a rk r a nge cl ass ific a tion r a nge on r a nge detection time output voltage s oft s t a rt v time t2p ( 8 02. 3a t) v t2p s t ab le b efore o u tp u t s oft- s t a rt am04509 8 v1
pm8803 pd interface doc id 018559 rev 2 21/34 4.4 undervoltage lockout after classification is completed, the pse raises the voltage to provide the power devices with the negotiated power. during the transition from low to operating voltage, the internal uvlo is released and the hot-swap mosfet is activated, initiating the inrush sequence. the pm8803 implements the uvlo mechanism by setting 2 internal thresholds on the voltage across the vdd-vss pins; one is to activate the hot-swap (v uvlo_r ), while the other is to switch off the hot-swap mosfet upon detection of a supply voltage drop (v uvlo_f ) from normal operating conditions. no additional external components are required to comply with the ieee requirements. the thermal protection alarm overrides the gate driving of the mos, immediately switching off the mos itself in case of device overheating. the hot-swap is bypassed also in auxiliary source topology, supplying directly the pwm section of the pm8803 and bypassing the hot- swap mosfet. 4.5 inrush and dc current limiting once the detection and classification phases have been successfully completed, the pse raises the voltage across the ethernet cable. when the voltage difference between vin and vss is greater than the v uvlo_r threshold, the internal hot-swap mosfet is switched on and the dc/dc input capacitance is charged in a controlled manner. during the inrush phase, the current is limited to 140 ma. when the rtn voltage falls below 1.5 v, an internal signal (pgood in figure 3 ) is asserted to activate the dc/dc section. figure 9. line transient response ch1: rtn - vss, ch2: vdd - vss, ch3: iinput, ch4: 5vout (with offset) am045099v1
pd interface pm8803 22/34 doc id 018559 rev 2 this feature is active only when working from an input voltage with a "frontal" connection, that must use the hot-swap mosfet; this voltage could be from the poe interface or from an external auxiliary adapter connected before the internal hot-swap mosfet. if the auxiliary source is connected after the hot-swap mosfet, it will be opened and this feature is disabled, allowing the converter to work with a low-voltage auxiliary source. the pgood comparator includes hysteresis to allow the pm8803 to operate near the current limit point without inadvertently disabling it. the mosfet voltage must increase to 12 v before pgood is deasserted. this feature will also allow withstanding positive line transients of up to 12 v without stopping dc/dc normal operations as shown in figure 9 . the line transient is managed by the pwm section, adjusting its operating parameters accordingly without shutting down the output voltage. the input current during the transient is controlled by the hot-swap mosfet at the dc current limit. after pgood assertion, a comparator on the gate of the hot-swap mosfet controls the transition between the 140 ma to the programmed dc current limit, with a 2 v threshold. the comparator is needed to ensure that the charge of the dc/dc input capacitor is completed, avoiding current spikes on the last portion of the charge. the pm8803 provides a default continuous current limitation of 640 ma. this is achieved by leaving the pin dccl floating. a different dc current limit can be set by connecting a resistor r dc between dccl and vss whose value can be obtained by the following equation: figure 10. dc current vs. r dc r dc k [] 22400 i dc ma [] ----------------------- = 20 120 220 3 20 420 520 620 720 8 20 920 1020 1120 r dc [kohm] i dc [ma] 20 40 60 8 0100 120 140 160 am045100v1
pm8803 pd interface doc id 018559 rev 2 23/34 this limitation is active after the in-rush phase is completed. the useful programming range for the current limitation is between 140 ma and 1 a. the practical resistor value range is between 22 k and 150 k . 4.6 high-voltage startup regulator the pm8803 embeds a high-voltage startup regulator to provide a controlled reference voltage of 8.0 v to the internal current mode pwm controller during its startup phase. the regulator output is connected to the vc pin as well as to the dc/dc section in normal isolated topology, the vc pin is diode-connected to the auxiliary winding of the transformer used for the flyback or forward configuration. when the voltage from the transformer exceeds the regulated voltage, the high-voltage regulator is shut off, reducing the amount of power dissipated inside the pm8803. in more detail, when the voltage from the auxiliary winding exceeds 8.0 v, the regulator resets its intervention threshold to 7 v. in this way, a loosely regulated voltage from the auxiliary winding is allowed without current-sharing with the internal regulator. in the meantime, if the auxiliary voltage fails, the internal regulator takes over without losing dc/dc control. the uvlo threshold on vc is 6.0 v typically: at this voltage the dc/dc controller operations are stopped and the outputs frozen in low state. while the external auxiliary voltage has to be chosen higher than 8.0 v to take advantage of the auxiliary winding, it must be also lower than 16 v for all operating conditions, to avoid the intervention of the internal protection clamp. a capacitor in the range of 220 nf-10 uf must be connected to dc/dc ground for stability. for applications with high current drawn from vc, large capacitance should be used (e.g. 10 f) in order to avoid converter switch-off during the startup phase. a vc uvlo mechanism monitors the level of voltage on the vc pin. when vc voltage exceeds the vc uvlo_r, the pwm controller is enabled and it remains enabled until the vc voltage drops below its vc uvlo_f value. when an auxiliary winding is not used, the internal hv regulator uvlo threshold is set at 6.6 v and the current limit is set at 20 ma typ. this value includes the current internally drawn to bias the dc/dc controller, the gate drivers, the vb bias regulator and the external components that may be connected to the vc and vb pins. notice that using the hv regulator without the auxiliary winding increases the internal power dissipation, and, when operating at high ambient temperature, may lead the device to go into thermal shutdown.
pd interface pm8803 24/34 doc id 018559 rev 2 4.7 5 v bias regulator the pm8803 features an accurate 5 v output regulator, which can be used to bias the dc/dc feedback network and the optocoupler connected to the microcontroller. a capacitor in the range of 100 nf - 2.2 f must be connected to artn for stability. the regulator current is supplied from the vc pin, to take advantage of the more efficient bias from the auxiliary winding. this means that the current drawn from the vb pin must be taken into account to evaluate the maximum current drawn from the vc pin the current drawn from the vb pin must be limited to 10 ma maximum. the vb regulator is also able to accept injected current up to 1 ma without losing voltage regulation.
pm8803 pwm controller doc id 018559 rev 2 25/34 5 pwm controller 5.1 oscillator the internal oscillator frequency can be programmed by connecting an external resistor r t between the frs and artn pins. the relationship between the oscillator frequency f osc and the r t resistor is: the pwm switching frequency is equal to the programmed oscillator frequency. the useful range for r t is between 20 k to 200 kohm figure 11. pwm frequency vs. r t 5.2 delay time control the delay between the rising edge of gat2 and gat1 waveforms can be set by putting a programming resistor r dt between dt and agnd or vb. the relationship between the delay time and the r dt resistor is: f osc khz () 25000 3k r + t k () ------------------------------------ - = 0 100 200 300 400 500 600 700 800 900 1000 1100 0 20 40 60 80 100 120 140 160 180 200 220 240 f osc [khz] r t [kohm] am045101v1 t del ns () 1.6r dt kohm () =
pwm controller pm8803 26/34 doc id 018559 rev 2 the same delay time is set between the gat1 falling edge and the subsequent gat2 falling edge. the useful range for r dt is between 5 k to 200 kohm. a resistor should always be connected to this pin. figure 12. delay time vs. r dt figure 13. timing relationship between output drivers as a function of dt am045102v1 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 dt [ns] r dt [kohm] gat2 gat1 dt dt am04510 3 v1
pm8803 pwm controller doc id 018559 rev 2 27/34 5.3 soft-start the dc/dc section of the pm8803 features an internal, digitally controlled, soft-start to make sure that output voltage ramps up in a safe and controlled manner. at the startup of the converter, the input voltage of the pwm comparator (ctl pin) is clamped to a value which is increased cycle by cycle until it reaches the regulation voltage. this results in a converter duty-cycle increasing from zero to the operative value in 4096 switching periods maximum. taking into account that the output voltage will start to increase only when the ctl pin is higher than 1 v, effective duration of the output voltage soft-start ramp can be estimated with the following formula: 5.4 pwm comparator / slope compensation in typical isolated operations, current is sensed on a sense resistor rs put between the source of the primary side mos and the rtn pin. the pwm comparator produces the pwm duty cycle by comparing the rs ramp signal on cs with an error voltage derived from the error amplifier output. the error amplifier output voltage at the ctl pin is attenuated by a 4:1 resistor divider before it is presented to the pwm comparator input. the pwm duty cycle increases with the voltage at the ctl pin. the controller output duty cycle reduces to zero when the ctl pin voltage drops below approximately 1 v. for duty cycles greater than 50%, current mode control loops are subject to sub-harmonic oscillation. the pm8803 fixes the maximum duty cycle at 80% and implements a slope compensation technique consisting of adding an additional fixed slope voltage ramp to the signal at the cs pin. this is achieved by injecting a 45 a sawtooth current into the current sense signal path on an integrated 2 k resistor. additional slope compensation may be added by increasing the source impedance of the current sense signal with an external resistor between the cs pin and the source of the current sense signal. the net effect in this case is to increase the slope of the voltage ramp at the pwm comparator terminals. 5.5 current limit the current sensed through the cs pin is compared to two fixed levels of 0.5 v and 0.7 v. the lower level is used to perform a cycle-by-cycle current limit, terminating the pwm pulse. if the overload persists for a duration longer than 4096 switching periods, the pwm is shut down for the same duration before beginning a new soft-start. at 250 khz the allowed overcurrent duration is about 16 ms. t ss ms [] 4096 f osc khz [] ------------------------------ ctl v [] 1v ? 4v ---------------------------------- ? =
pwm controller pm8803 28/34 doc id 018559 rev 2 when a severe overcurrent occurs, like a short-circuit of an internal power component, and 0.7 v level is reached on cs, the gate driver is instantaneously shut down and a new soft- start is performed after 4096 switching periods. in case of persistent severe overcurrent, the control logic tries 4 cycles of fast hiccup before completely shutting down the pwm controller. to restart the device, after removing the cause of the overcurrent, vdd must be reduced below the uvlo level. figure 14. overload (left) and short-circuit (right) behavior ch1: ctl signal, ch2: 5vout, ch3: i input 5.6 thermal protection the pm8803 thermal protection limit is set to 160 c on the junction temperature and is always active. when this threshold is exceeded, the hot-swap mosfet is opened and the pwm controller is switched off. when the junction temperature goes below about 130 c, the converter will start automatically, without recycling the input voltage. am045104v1
pm8803 auxiliary sources doc id 018559 rev 2 29/34 6 auxiliary sources the majority of powered devices is designed to work with power from either a poe network or auxiliary sources. even though having both sources simultaneously connected is not the normal operating case, the presence of an auxiliary supply allows pds to be used also when the poe is not available or not sufficient. different alternatives are available for connecting auxiliary sources to the poe section of a pd device. auxiliary sources can be connected prior to the hot-swap mosfet, after the hot- swap mosfet or even at the output of the dc/dc converter. all the above-mentioned methods are available with the pm8803. both figure 1 and figure 2 show simplified application schematics where auxiliary sources can be connected either prior (front) or after (rear) the internal hot-swap mosfet (vdd and rtn) making use of a resistor divider between the external source and respectively sp or sa pins. connection of the wall adapter prior to the internal hot-swap mosfet has a limitation on the voltage of the adapter itself, since it is seen as an alternative of the poe line and the embedded dc/dc section would be activated only when its value is above the uvlo_r threshold. if the voltage on the sp pin is above 1.1 v, the internal uvlo threshold is bypassed and the pm8803 operates with voltage as low as 15 v typical. the current flowing into the hot-swap mosfet will be limited by a dual threshold: typically140 ma during the inrush phase, and a user programmable value (dccl pin) for the rest of the phases. priority of one source over another cannot be guaranteed by design, since it depends on timings of insertion and the value of the poe line with respect to the auxiliary. if, for example, the poe connection is already established, the auxiliary source cannot prevail unless its value is higher than that of the poe after the diode bridge. please note that with the use of a low-voltage adapter applied before the hot swap frontal connection, the max power drawn could be evaluated as ( vin - vd ) x imax; in case of a 15 v adapter the input power will be limited to about (15 - 0.5) x 1 a = 14.5 w, much lower than the available power from the poe connection. high-power systems must use high-voltage power adapters, with voltage at 48 v, and rear connections, not to be limited by the internal dc current limitation. both figure 1 and figure 2 show simplified application schematics where auxiliary sources are also connected after the internal hot-swap mosfet (vdd and rtn). this connection, together with the resistor divider on the sa pin, allows priority of the external source with respect to the poe. indeed, if the voltage of this pin is above the value of 1.20 v, the pm8803 will disable its pd interface section and enable the dc/dc section only. the internal hot- swap mosfet will be opened. depending on the value of the auxiliary source, the resistor divider must be dimensioned in order to have voltage on the sa and sp pins above their thresholds but still below their maximum operative value of 3.3 v specified in ta bl e 3 . figure 15 depicts a smooth transition between a poe and a wall adapter whose voltage is 5 v higher than the poe voltage.
auxiliary sources pm8803 30/34 doc id 018559 rev 2 figure 15. smooth transition from poe to auxiliary source ch1: vss-rtn, ch2: sa, ch3: iinput, ch4: 5vout the minimum operative voltage for auxiliary sources is 13 v, thus allowing the use of a 15 v typ. +/-5% power adapter. the internal logic will enable operations of the pwm controller only if the input voltage is over the signature threshold (10.8 v typ, 10.3 v -11.3 v range). note that inrush current in this case is not limited and an external solution must be found. the simplest solution is to put a low value resistor in-series, but this lowers the converter?s efficiency. a more efficient solution is the use of a mosfet as the power switch, able to limit the current during the charging phase, and to add only a few m in-series during normal operation. no dc current limit is foreseen for the rear connection, since the current will not be flowing through the hot-swap mosfet. cycle-by-cycle, overcurrent protection and thermal protection are instead always active, as well as when the voltage on the sa pin is above 1.20 v. the t2p signal will remain high (de-asserted) if a rear auxiliary source is connected. if the t2p signal was asserted when the auxiliary source was connected, it will be turned off; its status is stored unless the input voltage drops. so if the pse stays connected until the auxiliary source is removed, the t2p indication turns on again when the wall adapter is disconnected. the removal of the external auxiliary source such as a wall adapter usually is followed by a system reboot because the pse needs some time to re-detect the pd. if a rear auxiliary connection (using the sa pin) is foreseen in the converter design, it is suggested to move the 0.1 f capacitor required by the ieee802.3at standard from the input (vdd to vss ) to the the internal hot-swap mosfet (vss to gnd) . alternatively, split the 0.1 f in two capacitors of 47 nf: one placed at the input terminal, the second one across the hot-swap mosfet. am045105v1
pm8803 package mechanical data doc id 018559 rev 2 31/34 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 8. htssop20 mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.2 0.047 a1 0.15 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 6.4 6.5 6.6 0.252 0.256 0.260 d1 4.1 4.2 4.3 0.161 0.165 0.169 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.5 0.169 0.173 0.177 e2 2.9 3.0 3.1 0.114 0.118 0.122 e 0.65 0.0256 k 0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030
package mechanical data pm8803 32/34 doc id 018559 rev 2 figure 16. htssop20 mechanical drawing gauge plane 7292297_c
pm8803 revision history doc id 018559 rev 2 33/34 8 revision history table 9. document revision history date revision changes 10-mar-2011 1 initial release. 07-nov-2012 2 document status promoted from preliminary data to production data. minor text changes.
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